$1.$ Micro$-$operations include the data transferring

A$.$ Into or out of a register.

B$.$ Between register to register.

C$.$ Between register to external bus.

D$.$ All of the above.

$2.$ The set of microinstructions that describe the behaviour of the Control Unit is stored in

A$.$ Control memory.

B$.$ Hardwired circuits.

C$.$ Instruction register.

D$.$ None of the above.

$3.$ Which of the following statement is TRUE about Pipelining?

A$.$ It is used for direct mapping of control memory address.

B$.$ It is used to reduce the percentage of idle components.

C$.$ It is used for microprogramming.

D$.$ None of the above.

$4.$ The problem of data dependency occurs when Instruction $1$ provides an input to Instruction $2$ in the pipeline architecture. The problem can be solved using

A$.$ Hardware interlocks.

B$.$ Operand forwarding.

C$.$ Both A and B$.$

D$.$ None of the above.

$2$

SCR$2033/$SCR$1043/$SCSR$1043/$SCE$3103$

$5.$ The conflict of resources can occurs in the Pipelining when

A$.$ Execution time is longer than the fetch time.

B$.$ Two segments need to access memory at the same time.

C$.$ NOP occurs.

D$.$ All of the above.

$6.$ Which of the following statement is FALSE regarding the basic concept of Memory?

A$.$ The number of bits in memory address determines the capacity of memory location.

B$.$ Memory chips can be located internally and externally of a computer.

C$.$ Memory access time is referred to the time taken to get the valid data starting from the CPU presenting the data on the data bus.

D$.$ Memory hierarchy keeps the memory that is frequently accessed high up on top of the pyramid.

$7.$ Which of the following describes DRAM?

I. Larger memory than SRAM

II$.$ Volatile

III. Used as cache memory

IV$.$ Smaller access time than SRAM

A$.$ I and II$.$ C$.$ I, II and IV$.$

B$.$ I, II and III. D$.$ All of the above.

$8.$ The following statements are TRUE about the disadvantages of High$-$order Interleaving $($HOI$)$ EXCEPT

A$.$ HOI causes memory conflicts in case of pipelined or vector processors.

B$.$ HOI is useful only in one single user multitasking system.

C$.$ HOI memory cycle time is much greater than pipelined clock time.

D$.$ HOI memory is easy to be extended by the addition one or more memory modules.

$3$

SCR$2033/$SCR$1043/$SCSR$1043/$SCE$3103$

$9.$ Choose the BEST statement to describe Cache memory.

A$.$ Inexpensive in cost with large capacity of location.

B$.$ Usually located near to main memory.

C$.$ It keeps a copy of the most frequently used data from the main memory.

D$.$ It sits on top of the memory hierarchy.

$10.$ Given the memory word size is $32$ bit and a block size is $4$K words. Find the memory capacity if the total blocks is $512$ blocks.

A$.32$Mbits.

B$.64$Mbits.

C$.64$Kbits.

D$.128$Kbits.

$11.$ Which is the CORRECT statement for multiplexed bus lines?

A$.$ Multiplexed bus line is an approach where different bus can be used to transfer both data and address.

B$.$ Multiplexed bus lines require more than one cycle to transmit data and address information.

C$.$ Multiplexing bus can maximize the number of wires in a bus system.

D$.$ Multiplexed bus lines can increase the overall performance of memory access time.

$12.$ I$/$O Module is able to detect errors. One of the common errors is paper jammed. Which category does this error falls into?

A$.$ Electrical malfunction.

B$.$ Mechanical malfunction.

C$.$ Transmission error.

D$.$ Chemical malfunction.

$4$

SCR$2033/$SCR$1043/$SCSR$1043/$SCE$3103$

$13.$ Choose the CORRECT statement about Interrupt Driven I$/$O$.$

A$.$ Interrupts can occur without the CPU initiating any operation.

B$.$ CPU cannot perform other tasks while waiting for the I$/$O device to get ready.

C$.$ When interrupt occurs, the processor saves the context of the current program and processes the interrupt.

D$.$ I$/$O module must receive interrupt acknowledgement before data can be transferred from or to I$/$O device.

$14.$ An I$/$O Control command were used

A$.$ To obtain a data from peripheral and place it in internal buffer.

B$.$ To take a data from the data bus and transmit it to the peripheral.

C$.$ To activate a peripheral and tell it what to do$.$

D$.$ As a software routine written by the user to handle the interrupt polling.

$15.$ Below are the major functions of an I$/$O Module EXCEPT

A$.$ Data Buffering.

B$.$ Control and timing.

C$.$ Processor communication.

D$.$ Error correction.

$16.$ Given AX$=12510.$ Determine the final value of AX after the following codes are executed.

INC AX

INC AX

NEG AX

A$.01$C$8$h

B$.01$C$9$h

C$.$ FF$83$h

D$.$ FF$84$h

$5$

SCR$2033/$SCR$1043/$SCSR$1043/$SCE$3103$

$17.$ What is the content of AL and overflow flag $($OF$)$ after the following codes are executed.

MOV AL$,7$Fh

ADD AL$,1$

A$.$ AL$=7$Fh$,$ OF$=0$

B$.$ AL$=80$h$,$ OF$=0$

C$.$ AL$=7$Fh$,$ OF$=1$

D$.$ AL$=80$h$,$ OF$=1$

$18.$ Choose the BEST statement to describe the following codes.

$.$code

CALL CLRSCR

MOV EAX, $500$

CALL Delay

CALL DumpRegs

A$.$ Clear the screen, delay the program for $500$ milliseconds.

B$.$ Clear the screen, delay the program for $500$ milliseconds, and dump the registers and flags.

C$.$ Branching to subroutine CLRSCR$,$ delay the program for $500$ millisecon