$1.$ Objectives:

To design and verify a simple pipelined RISC processor in Verilog

$2.$ Processor Specifications

$1.$ The instruction size and the words size is $32$ bits

$2.1632-$bit general$-$purpose registers: from R$0$ to R$15.$

$3.32-$bit special purpose register for the program counter $($PC$)$

$4.32-$bit special purpose register for the stack pointer $($SP$),$ which points to the topmost empty element of

the stack. This register is visible to the programmer.

$5.$ The program memory layout comprises the following three segments:

$($i$)$ Data segment

$($ii$)$ Code segment

$($iii$)$ Stack segment. It is a LIFO $($Last in First out$)$ data structure. This machine has explicit instructions

that enables the programmer to push$/$pop elements on$/$from the stack. The stack stores the

return address, registers$$ values upon function calls, etc.

$6.$ Four instruction types $($R$-$type, I$-$type, J$-$type, and S$-$type$).$

$7.$ Separate data and instructions memories

$8.$ Byte addressable memory

$9.$ Big endian byte ordering

$10.$ You need to generate the required signals from the ALU to calculate the condition branch outcome

$($taken$/$ not taken$).$ These signals might include zero, carry, overflow, etc.

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$3.$ Instruction Types and Formats

As mentioned above, this ISA has four instruction formats, namely, R$-$type, I$-$type, J$-$type, and S$-$type. These four

types have a common $6-$bit opcode field, which determines the specific operation of the instruction

R$-$Type $($Register Type$)$

Opcode$6$ Rd$4$

Rs$14$

Rs$24$ Unused$14$

$4-$bit Rd: destination register

$4-$bit Rs$1$: first source register

$4-$bit Rs$2$: second source register

$14-$bit unused

I$-$Type $($Immediate Type$)$

Opcode$6$ Rd$4$

Rs$14$

Immediate$16$ Mode$2$

$4-$bit Rd: destination register

$4-$bit Rs$1$: first source register

$16-$bit immediate: unsigned for logic instructions, and signed otherwise.

$2-$bit mode: this is used with load$/$store instructions only, such that

$00$: no increment$/$decrement of the base register

$01$: post increment the base register

$01$: pre increment the base register

$11$: post decrement the base register

For example:

lw Rd$,$ imm $($Rs$1)$ # Reg$[$Rd$]=$ Memory $[$Reg$[$Rs$1]+$ sign$\_$extend$($imm$)]$

Mode Value Action

$00$ lw Rd$,$ imm $($Rs$1)$ # No inc$/$dec of the base register

$01$

LW$.$PRI Rd$,$ imm $($Rs$1)$ # load word pre$-$increment

Before the address is sent to the memory, the base register is incremented

Reg$[$Rs$1]=$ Reg$[$Rs$1]+4$

It is incremented by four because lw loads one word and the word size is $4$ bytes

$10$

LW$.$POI Rd$,$ imm $($Rs$1)$ # load word post$-$increment

After the address is sent to the memory, the base register is incremented

Reg$[$Rs$1]=$ Reg$[$Rs$1]+4$

$11$

LW$.$POD Rd$,$ imm $($Rs$1)$ # load word post$-$decrement

After the address is sent to the memory, the base register is decremented

Reg$[$Rs$1]=$ Reg$[$Rs$1]-4$

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J$-$Type $($Jump Type$)$

This type includes the following instruction formats. The opcode is used to distinguish each instruction

jmp L # Unconditional jump to the target L$.$

call F # Call the function F$.$ F is a label.

# The return address is pushed on the stack

The target address is calculated by concatenating the most significant $6-$bit of the current PC with the $26-$bit

offset

Opcode$6$

Jump Offset$26$

ret # return from a function.

# the next PC will be the top element of the stack

Opcode$6$ Unused$26$

jr Rd # jump to the target address stored in the register Rd

call.r Rd # Call the function whose address is stored in the register Rd

Opcode$6$ Rsd

$4$ Unused$22$

S$-$Type $($Stack$)$

$4-$bit Rd: destination register

$4-$bit Rs$1$: first source register

Opcode$6$ Rd$4$

Rs$14$ Unused$18$

push$\mathrm{.}1$ Rd # push one. push the value of Rd on the top of the stack

push.m Rd$,$ Rs$1$ # push many. Push the values of the registers in the range

#Rd to Rs$1$ in order on the top of the stack

pop$\mathrm{.}1$ Rd # pop one. Pop the stack and store the topmost element in Rd

pop.m Rd$,$ Rs$1$ # pop many. Pop the top $($Rs$1$ Rd$)+1$ elements from the

# stack, and store the values of these elements in the

# registers from Rd to Rs$1.$

# The topmost element is stored in Rd$,$ and so on$.$

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$4.$ Instructions$$ Encoding

For simplicity, you are required to implement a subset only of this processor$$s ISA. The table below shows the

different instructions you are required to implement. It shows their type, the opcode value, and their meaning

in RTN $($Register Transfer Notation$).$ Although the instruction set is reduced, it is still rich enough to write useful

programs.

No$.$ Instr Meaning Opcode

Value

R$-$Type Instructions

$1$ AND Reg$($Rd$)=$ Reg$($Rs$1)$ & Reg$($Rs$2)000000$

$2$ ADD Reg$($Rd$)=$ Reg$($Rs$1)+$ Reg$($Rs$2)000001$

$3$ SUB Reg$($Rd$)=$ Reg$($Rs$1)-$ Reg$($Rs$2)000010$

$4$ OR Reg$($Rd$)=$ Reg$($Rs$1)$ I Reg$($Rs$2)000011$

I$-$Type Instructions

$5$ ANDI Reg$($Rd$)=$ Reg$($Rs$1)$ & Imm$16000100$

$6$ ADDI Reg$($Rd$)=$ Reg$($Rs$1)+$ Imm$16000101$

$7$ LW Reg$($Rd$)=$ Mem$($Reg$($Rs$1)+$ Imm$16$

$)000110$

$8$

LW$.$PRI

Reg$($Rd$)=$ Mem$($Reg$($Rs$1)+4+$ Imm$16$

$)$

Reg$[$Rs$1]=$ Reg$[$Rs$1]+4$

$000111$

$9$

LW$.$POI

Reg$($Rd$)=$ Mem$($Reg$($Rs$1)+$ Imm$16$

$)$

Reg$[$Rs$1]=$ Reg$[$Rs$1]+4$

$001000$

$10$

LW$.$POD

Reg$($Rd$)=$ Mem$($Reg$($Rs$1)+$ Imm$16$

$)$

R