1-) Processor Cycle Time Determination:

Assume the following latencies for the logic blocks in Figure 4.17 from the textbook.

I-Mem, Adder, MUX ,ALU, Reg Read, D-Mem, SignExtend, ShiftLeft-2, Control ,ALU Control, AND gate, respectively 200ps, 70ps, 20ps, 90ps, 90ps, 250ps, 10ps, 5ps, 40ps, 20ps, 10ps

a. Identify and quantify (i.e., give the path through the blocks and the time for that path) the worst-case path for each of the following: an arithmetic R-format instruction, a lw instruction, and a conditional branch instruction.

b. Rank the following design approaches in terms of which improve the cycle time the most. You must justify your ranking.

i. Developing an "extra fast adder" that reduces the Adder and ALU latencies

ii. Changing the ISA memory addressing mode to directly use the base registers value (i.e., no offset addition)

iii. Designing a lower-latency control unit.