= 1 = Q3: Assume multiple cycle MIPS: Assume that x and y are arrays of words and the base address of x is in R1 and the base address of y is in R2. If ALU instructions (add and addi) take 1 cycle to execute, load/store (lw and sw) take 5 cycles to execute, and the branch (bne) instruction takes 3 cycles to execute; addl To, zero, zero # TO = i = 0+0 = 0 add2 T1, R1, zero # T1 = address of x[i] add3 T2, R2, zero # T2 address of y[i] add4 T3, zero, 101 Loop: lw T4, 0 (T2) # Load T4 with M[T2+0] value add5 T5, T4, C # C is a constant value SW T5, 0 (T1) # Store T5 to M[T1+0] addil TO, TO, 1 addi2 T1, T1, 4 addi3 T2, T2, 4 240: bne TO, T3 -7 # Goes to Loop when taken 244: add6 TO, TO, 100 248: add7 T1, T1, 10 I a. How many instructions are executed during the running of the following code? b. How many cycles are needed to execute the code (all iterations)? C. Calculate the average CPI (cycles per instruction)? d. Calculate the Branch Target Address (loop) when branch is taken? e. Identify the Read after Write (RAW) hazards that exist among the Loop instructions (only)