1. Suppose you were given the opportunity to redesign the memory mapping hierarchy for a new CPU. We have seen that 4KB pages seem a little small. Suppose you made the pages 217= 131072 bytes. 1. How many 64-bit addresses would fit in such a page? Example from book: 4096-byte page = 212 and 8-byte address =23, so 212/23=29=512. 2. How many bits would be required for the addressing of the page table? 3. How would you break up the bit fields of the virtual addresses? 2. Suppose a virtual memory address is 0123456789012. Divide this address into the 4 different page table parts and the page offset. 3. Suppose a virtual memory address is 0123456789012. Suppose this happens to be an address within a 2 MB page. What is the page offset for this address