1.) This register can be used to mask the channels of DMA using one write operation a. Single Mask b. Status c. Command d. None of the above

2.) The address of I/O device is communicated using a. Data buses b. Data Lines c. Address bus d. Status lines

3.) I/O command type a. Read b. Control c. Test d. All the above

4.) Processor communication does not involve a. Command decoding b. Status reporting c. Error correcting d. None of the above