1. We have a 5-stage pipeline:

IF instruction fetch

ID instruction decode and read registers

EX execute instruction or calculate address

MEM access memory

WB write results to registers

For each of the following blocks of code, (i) determine if there are any data hazards. Support this with a diagram showing the instructions moving through the pipeline. Show the hazards on the diagram. (ii) if there are pipeline hazards, for how many stages would the pipeline stall? (iii) if there are pipeline hazards, reorder the code given to avoid them without introducing new hazards while still accomplishing the same result. Dont add any additional code either.

(a)

ADD R1, R2, R3

STR R2, [R5]

STR R3, [R6]

MUL R4, R1, R2

ADD R7, #4

(b)

ADD R2, #4

LSL R4, #5

LDR R1, [R2]

LDR R3, [R2]

SUB R5, #2

SUB R6, #3

1. We have a 5-stage pipeline IF - instruction fetch ID instruction decode and read registers EX - execute instruction or calculate address MEM- access memory WB write results to registers For each of the following blocks of code, (i) determine if there are any data hazards. Support this with a diagram showing the instructions moving through the pipeline. Show the hazards on the diagram (ii) if there are pipeline hazards, for how many stages would the pipeline stall? (iii) if there are pipeline hazards, reorder the code given to avoid them without introducing new hazards while still accomplishing the same result. Don't add any additional code either (a ADD R1, R2, R3 STR R2, [R5] STR R3, [R6] MUL R4, R1, R2 ADD R7 , #4 ADD LSL R4, #5 LDR R1, [R2] LDR R3, [R2] SUB R5 , #2 SUB R6 , #3 (b) R2 , #4