1-) Why do branches use PC-relative addressing rather than the pseudo-direct addressing that jumps use? [Hint: Remember that neither addressing mode provides direct access to the full 32-bit addressing space.]

2-) Going on the principle that threes a crowd, your boss tasks you with writing a report detailing the feasibility of removing the J-format from MIPS. To write this, you must consider how you would implement the now pseudo instruction, j label. Provide a functionally-equivalent implementation using MIPS ISA instructions that use only the I- and R-formats.

3-) (a) Disassemble the following MIPS machine instruction (i.e., list the instructions mnemonic and the types and decimal values of the operand fields). Show your work!

0x1000FFFF

(b) If this specific instruction instance (i.e., specific assignment of operands) were implementing a pseudo instruction, what would you name it and what high-level functionality is it implementing?

4-) Your hack of a lab partner has generated the adjacent MIPS assembly function, BAD, to help test your processor. Of course, it doesnt follow the MIPS ABI calling conventions that you carefully followed when writing the functions that call and are called by this function. In order to test your processor design and pass 381 you must now fix this code. (a) Identify which registers must you allocate space for on the stack? Justify why your are allocating space for each register. (b) Identify which of these registers you will actually have to write to the stack during this function. Justify why you are writing each register.

1 BAD:

2 add $t1, $a0,$zero

3 lw $t0, 0($t1)

4 sw $a2, 0($t1)

5 xori $t2, $a2, 0x0F

6 add $s0, $t2, $a3

7 sub $s1, $t2, $s0

8 addiu $a0, $a0, 1

9 jal GOOD

10 add $t1, $v1, $t0

11 sw $v0, 0($t1)

12 add $v0, $a1, $t2

13 add $v0, $v0, $s1

14 jr $ra