1. Write a VHDL std logic code description for a counter 6, 1,4, 0, 3 then repeat. entity partl is Port ( clk: in std logic; : out std_logic_vector(2 downto 0)) end partl architecture Behavioral of part1 is TYPE state_type is (one,two,five,seven); Signal state: state type; begin process begin if then CASE state IS when . state