1. Write the verilog code and testbench for 2:4 decoder using data flow modeling, with active high output. (Hint: part of code is written below; A is input, and D is output.) Complete the truth table. (-A[1]&-A[0]); assign D[0] assign D[1] (-A[1]&A[0]); assign D[2] (A[1]&-A[0]); assign D[3] (A[1]&A[0]); T A1 A0 DO D1 D2 D3 0 1 00 1 1 la 0 1