10. For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.

Tag	Set	Block Offset	Byte Offset
31-10	9-5	4-2	1-0

a. What is the cache block size?

b. How many blocks does the cache have?

c. What is the cache capacity?

d. Starting from power on, the following word-addressed cache references are recorded. 0, 4, 16, 132, 140, 160, 12, 164 i. How many blocks are replaced? j. What is the hit ratio, assuming the cache is initially empty?