(10 points) For this question, consider the memory below (the memory is similar to that in Assignment 3, but with the contents of some of the latches changed). The memory consists of 4 locations, each location storing 3 bits using 3 D-latches. The figure shows the value initially stored in each D-latch in this circuit. MAR (memory address register) consists of 2 flip-flops, and MDR (memory data register) consists of 3 flip-flop. MAR and MDR are latched at the start of each clock cycle based on the values on their corresponding input lines (i.e., MAR and MDR are both "write-enabled" in each clock cycle in this question). The inputs of the MAR are directly connected to the outputs Q2 and Q1 from the memory (NOTE: Inputs of the MAR are NOT connected to the outputs of MDR). Inputs A1 and A0 to the memory are connected to the outputs of register MAR. Assume input WE for the memory to be 0 for this question. A memory read is initiated every cycle, and the data is available by the end of that cycle. The values of inputs D2D1D0 are not relevant to the answer of this question (but if needed, you may assume that those inputs are 000). Just before the start of cycle 1, MAR contains 11 and MDR contains 110. (a) What do MAR and MDR contain just BEFORE the end of cycle 1 ? MAR MDR (b) What do MAR and MDR contain just before the end of cycle 2? MAR MDR (c) What do MAR and MDR contain just before the end of cycle 3 ? MAR MDR