10. Suppose the memory cells at addresses 00 to 08 in the machine described in Appendix C contain the bit pattems described in the following table. If we start the machine with its program counter containing 00 . (1) List the addresses of the memory cells that contain the program that will be executed. (2 points) (2) Record the contents of the Instruction Register, Program Counter, the register 5, register 6 , and memory cell 08 as following. Then decode each instruction. (2 points each) (i) At the end of the fetch step of the 114 machine cycle Decode ( 3 points): (ii) At the end of the fetch step of the 2nd machine cycle Decode ( 3 points): (iii) At the end of the fetch step of the 3rd machine cycle Decode ( 3 points): (iii) At the end of the fetch step of the 4 th machine cycle IR Decode ( 3 points): (3) List the addresses of the memory cells that are used to hold data. ( 2 points)