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Write Verilog code for the counter-type ADC in Fig. 1 and verify the operation through waveform. The operation of the ADC is summarized below. The GATE passes the clock signal to the counter when a START trigger signal is received. The counter then starts counting until the output of DAC is equal/greater than the analogue input, VA. When the output of DAC is greater/equal to VA, the output of comparator is zero which turns off the GATE and the counter stops counting i.e. the clock is no more passed to the counter. The counter can then be reset before starting the next operation. Once the GATE is enabled and the counter starts, any change in START signal has no effect as long as the output of comparator is zero. Start Clock Gale Counter Digital Output D/A Analogue Converter Input, VA Fig. 1