[10/15/15/10/10]<1.4,1.5> One challenge for architects is that the design created today will require

several years of implementation, verification, and testing before appearing on the market. This means

that the architect must project what the technology will be like several years in advance. Sometimes,

this is difficult to do.

Problem

a) [10] <1.4> According to the trend in device scaling historically observed by Moores Law, the

number of transistors on a chip in 2025 should be how many times the number in 2015?

b) [15] <1.5> The increase in performance once mirrored this trend. Had performance continued to

climb at the same rate as in the 1990s, approximately what performance would chips have over

the VAX-11/780 in 2025?

c) [15] <1.5> At the current rate of increase of the mid-2000s, what is a more updated projection

of performance in 2025?

d) [10] <1.4> What has limited the rate of growth of the clock rate, and what are architects doing

with the extra transistors now to increase performance?

e) [10] <1.4> The rate of growth for DRAM capacity has also slowed down. For 20 years, DRAM

capacity improved by 60% each year. If 8 Gbit DRAM was first available in 2015, and 16 Gbit is

not available until 2019, what is the current DRAM growth rate?