10-C- 115-0 Instruction Figure 1: MIPS Datapath with Interstage Registers Exercise 1. [20 Marks] Consider the multi-cycle MIPS datapath presented in Figure 1, it shows 4 inter-stage registers: IF/ID, ID/EX, EX/MEM, and MEM/WB. Consider also the control signals presented in the diagram in blue. Assume the ALUOp control signal is 3 bits. Ignore control signals not shown i.e. the ones controlling forwarding). Determine the minimum size, in bits, of each of the four inter-stage registers. For part marks, ensure to include workings and not just the total values