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1.1 Assume that the inverter in the given circuit has a propagation delay of 5ns and the AND gate has a propagation delay of 10ns.

1.1 Assume that the inverter in the given circuit has a propagation delay of 5ns and the AND gate has a propagation delay of 10ns. Draw a timing diagram for the circuit showing X,Y, and Z. Assume that X is initially 0,Y is initially 1 , after 10nsX becomes 1 for 80ns, and then X is 0 again

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