(11) The truth table for the sum S and carry C0 outputs of a half-adder is shown in Table 4. Notice that the halfadder may be constructed from an Exclusive OR gate and an AND gate. The truth table for a full-adder is shown in Table 5. Deduce how a full-adder may be formed by cascading together three half-adders which may then be simplied to a circuit with two halfadders. Alternatively, derive the circuit of a fulladder by expressing its sum and carry outputs in terms of Exclusive OR functions. Connect up your full-adder using only NAN D and XOR gates in Logisim. Test the operation of your circuit. Table 4 Table 5 9