(1+1+1+1+1] (b) Consider the following 8051 interfacing problem. 8051 ADC0804 +5V Voc P2.5 P2.6 RD WR CLK D CLK IN P1.0 DO Vin(+) Vin() 10k POT A GND Vref/2 D GND P1.7 D7 P2.7 INTR CS The delay between consecutive analog to digital conversion will be dynamically adjusted. If the analog reading (Vanalog) goes >= VCC/2, delay is 40 ms while if goes