199 , 898 PE (25 points Use the accompanying state diagram for this prob. lem. In addition to an asynchronous active-low reset. X & Y are the inputs, Z is the output, and So is the reset state. Assume that all circuit inputs and outputs are declared as std.logic in the entity, and that the numeric.std library has been declared as well. P3(a) (5) Give a suitable VHDL entity for the state machine. 188 ( S 0100110 S, 00/1 199 , 898 PE (25 points Use the accompanying state diagram for this prob. lem. In addition to an asynchronous active-low reset. X & Y are the inputs, Z is the output, and So is the reset state. Assume that all circuit inputs and outputs are declared as std.logic in the entity, and that the numeric.std library has been declared as well. P3(a) (5) Give a suitable VHDL entity for the state machine. 188 ( S 0100110 S, 00/1