2) [10] Consider following loop: r2, e (r2) r2, re, LOOP r2, r2, r3 r2, 0 (r5) Loop: LW BEQ OR SW Assume that there is no delay slot and the nextPC in located in ID stage. Also assume that the loop is iterated for 100 times. Draw the pipeline diagram for the first 2 iterations a) CSE661 H4: ILP Due: 28/3/2018 b) How many cycles does is take to complete the instruction sequence? If a one bit branch predictor is used, which is initialized to N(i.e. branch not taken), how many correct and wrong predictions that it will produce? c) 2) [10] Consider following loop: r2, e (r2) r2, re, LOOP r2, r2, r3 r2, 0 (r5) Loop: LW BEQ OR SW Assume that there is no delay slot and the nextPC in located in ID stage. Also assume that the loop is iterated for 100 times. Draw the pipeline diagram for the first 2 iterations a) CSE661 H4: ILP Due: 28/3/2018 b) How many cycles does is take to complete the instruction sequence? If a one bit branch predictor is used, which is initialized to N(i.e. branch not taken), how many correct and wrong predictions that it will produce? c)