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2 . 3 Exercise 3 Change mode String bit LED circuit. Use Verilog HDL to model a state machine for a circuit that changes display

2.3 Exercise 3
Change mode String bit LED circuit.
Use Verilog HDL to model a state machine for a circuit that changes display mode of a bit string.
In initial, LEDs show the default 4-bit random string which is performed by a reset signal, example
string: 0011. And buttons in board will set the display mode as follow:
Logic Design with HDL - Semester 2222/3
Faculty of Computer Science and Engineering Department of Computer Engineering
Button 0: Mode Reset: Show the default 4-bit string on LEDs.
Button 1: Mode Circular Shift Left Ring : Shift 4-bit string to left in a ring every 1s.
Button 2: Mode Circular Shift Right Ring: Shift 4-bit string to right in a ring every 1s.
Button 3: Pause: Pause the current shifting string.
Draw a state diagram to illustrate the designed FSM. Student can use Moore or Mealy model.
Write a test bench to simulate the circuit and test the circuit on the Arty-Z7 board.
Hint: Students should do the following steps:
Partitioning the design into blocks, may draw a block diagram. Separate the state machine and the
string display logic.
Define the inputs, outputs of the FSM, then design the FSM.
Modeling the FSM using Verilog HDL. Use the FSMs outputs to control the string display.
Simulate and test the circuit on board. 2.3 Exercise 3
Change mode String bit LED circuit.
Use Verilog HDL to model a state machine for a circuit that changes display mode of a bit string.
In initial, LEDs show the default 4-bit random string which is performed by a reset signal, example
string: 0011. And buttons in board will set the display mode as follow:
Logic Design with HDL - Semester 222
Button 0: Mode Reset: Show the default 4-bit string on LEDs.
Button 1: Mode Circular Shift Left Ring : Shift 4-bit string to left in a ring every 1s.
Button 2: Mode Circular Shift Right Ring: Shift 4-bit string to right in a ring every 1s.
Button 3: Pause: Pause the current shifting string.
Draw a state diagram to illustrate the designed FSM. Student can use Moore or Mealy model.
Write a test bench to simulate the circuit and test the circuit on the Arty-Z7 board.
Hint: Students should do the following steps:
Partitioning the design into blocks, may draw a block diagram. Separate the state machine and the
string display logic.
Define the inputs, outputs of the FSM, then design the FSM.
Modeling the FSM using Verilog HDL. Use the FSM's outputs to control the string display.
Simulate and test the circuit on board.
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