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2 ) A synchronous sequential finite state machine with one input X and one output Z is to be designed. The output Z becomes logic

2) A synchronous sequential finite state machine with one input X and one output Z is to be
designed. The output Z becomes logic-l if a 3-bit binary number formed by three
consecutive bits on X is divisible by 3(most significant bit comes first). Otherwise, the
output Z is equal to logic-0. The circuit returns to its initial State if the output Z becomes
logic-l. You should e D flip-flops (YD). Example input-output sequence:
x: 001101110011000001
z: 000100100001001000

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