2. Draw a pipeline diagram utilizing the typical 5-stage IF, ID, EX, MEM, WB MIPS design for MIPS code below. Assume the processor has perfect branch prediction and can fetch any two instructions (not just consecutive instructions) in the same cycle. ADD R5, RO, RO BEQ R5, R6, End ADD R10, R5, R1 LW R11, 0(R10) LW R10, 1(R10) SUB R10, R11, R10 ADD R11, R5, R2 SW R10, 0(R11) ADDI R5, R5, 2 BEW RO, RO, Again BEQ R5, R6, End ADD R10, R5, R1 LW R11, 0(R10) LW R10, 1(R10) SUB R10, R11, R10 ADD R11, R5, R2 SW R10, 0(R11) ADDI R5, R5, 2 BEW RO, RO, Again BEQ R5, R6, End