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2. Draw the logic diagram of a four-bit register with four D flip-flops and four 4x1 multiplexers with mode selection S1 and So. The register
2. Draw the logic diagram of a four-bit register with four D flip-flops and four 4x1 multiplexers with mode selection S1 and So. The register operates according to the following function table. S1 0 0 SO 0 1 0 Register Operation Load parallel data Complement the four outputs Clear register to 0 (synchronous with the clock) No change 1 1 1 1
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