2. Pipeline Simulation For each of the modules from Figure 4.51 (page 304 of P&H) that are listed in the table below, specify what the inputs and outputs are in each cycle for the following code. You do not need to specify values for those modules, inputs, or outputs not listed in the table. Manually simulate (i.e., fill out the table) until the sw has completed (i.e., left the write-back stage). [Hint: the table already has the first couple of cycles filled out. If a value depends on an instruction before or after the code below, report it as X.] MemtoReg MUX Instruction Memory Register File ALU PCSrc MUX Op e-ALU result10 sub) Cycle Read Read data 1 WriteWrite Addr reg data 1oxooo00010 lui. X X X OxXXXXXXXX 0x000000140 X XX 0xXXXXXXXX0x00000018 0 X Ox000010010x10010000 X X XOxXXXXXXXX 0x0000001c 0 0x00000014 0x00000018sub..0x000x00000000 X Pipelined MIPS - Simulation Table] # Assume that $a0-3, $a1-1024, $a2-1023, $a3--1 # at the start of your manual simulation. # Assume that lui is supported by the lul operation in # the ALU and that the value shifted for lui is the B # input of the ALU (note that this is likely different # than your project implementation and that's OK) . # The following instructions start at address 0x00000010: lui $s0, 0x1001 addi $t0, zero, 42 sub $tl, $a0, $al xor $t2, $a2, $a3 ori $s0, $s0, 0x0040 beq $t0, $a3, Exit addi $t4, $zero, 0 sll $zero, $zero, 0 sw $t0, ($s0) Exit: # This label resolves to address 0x00000100 2. Pipeline Simulation For each of the modules from Figure 4.51 (page 304 of P&H) that are listed in the table below, specify what the inputs and outputs are in each cycle for the following code. You do not need to specify values for those modules, inputs, or outputs not listed in the table. Manually simulate (i.e., fill out the table) until the sw has completed (i.e., left the write-back stage). [Hint: the table already has the first couple of cycles filled out. If a value depends on an instruction before or after the code below, report it as X.] MemtoReg MUX Instruction Memory Register File ALU PCSrc MUX Op e-ALU result10 sub) Cycle Read Read data 1 WriteWrite Addr reg data 1oxooo00010 lui. X X X OxXXXXXXXX 0x000000140 X XX 0xXXXXXXXX0x00000018 0 X Ox000010010x10010000 X X XOxXXXXXXXX 0x0000001c 0 0x00000014 0x00000018sub..0x000x00000000 X Pipelined MIPS - Simulation Table] # Assume that $a0-3, $a1-1024, $a2-1023, $a3--1 # at the start of your manual simulation. # Assume that lui is supported by the lul operation in # the ALU and that the value shifted for lui is the B # input of the ALU (note that this is likely different # than your project implementation and that's OK) . # The following instructions start at address 0x00000010: lui $s0, 0x1001 addi $t0, zero, 42 sub $tl, $a0, $al xor $t2, $a2, $a3 ori $s0, $s0, 0x0040 beq $t0, $a3, Exit addi $t4, $zero, 0 sll $zero, $zero, 0 sw $t0, ($s0) Exit: # This label resolves to address 0x00000100