2. Pipeline Simulation For each of the modules from Figure 4.51 (page 304 of P&H) that are listed in the table below, specify what the inputs and outputs are in each cycle for the following code. You do not need to specify values for those modules, inputs, or outputs not listed in the table. Manually simulate (i.e., fill out the table) until the sw has completed (i.e., left the write-back stage). [Hint: the table already has the first couple of cycles filled out. Ifa value depends on an instruction before or after the code below, report it as X.] Instruction Memory Register File ALU PCSrc MUX MUX Cycle Op instr reg 1 Write Write reg data Addr Read data 1 ALU result10s sub) | 0x00000010 | lui | ? 0x00000014 XX X0xXXXxxxx 0x00000018O 3Ox00000018 sub.. 0x00 x0000 x x 1 x 0100001001 sli | 0x100 10000 | X | X X OxXXXXXXXX | 0x0000001 0 Pipelined MIPS-Simulation Table # Assume that $a0 3, $al-, 1024, $a2 1023, $a3 -1 # at the start of your manual simulation. # Assume that lui is supported by the lui operation in # the ALU and that the value shifted for lui is the B # input of the ALU (note that this is likely different # than your project implementation and that's OK) # The following instructions start at address 0x00000010: lui $s0, 0x1001 addi $t0, $zero, 42 sub $tl, $a0, $al ori $s0, $s0, 0x0040 beq $to, $a3, Exit addi $t4, $zero, 0 sll ?zero, $zero, 0 sw $to, (s0) Exit: # This label resolves to address 0x00000100. 2. Pipeline Simulation For each of the modules from Figure 4.51 (page 304 of P&H) that are listed in the table below, specify what the inputs and outputs are in each cycle for the following code. You do not need to specify values for those modules, inputs, or outputs not listed in the table. Manually simulate (i.e., fill out the table) until the sw has completed (i.e., left the write-back stage). [Hint: the table already has the first couple of cycles filled out. Ifa value depends on an instruction before or after the code below, report it as X.] Instruction Memory Register File ALU PCSrc MUX MUX Cycle Op instr reg 1 Write Write reg data Addr Read data 1 ALU result10s sub) | 0x00000010 | lui | ? 0x00000014 XX X0xXXXxxxx 0x00000018O 3Ox00000018 sub.. 0x00 x0000 x x 1 x 0100001001 sli | 0x100 10000 | X | X X OxXXXXXXXX | 0x0000001 0 Pipelined MIPS-Simulation Table # Assume that $a0 3, $al-, 1024, $a2 1023, $a3 -1 # at the start of your manual simulation. # Assume that lui is supported by the lui operation in # the ALU and that the value shifted for lui is the B # input of the ALU (note that this is likely different # than your project implementation and that's OK) # The following instructions start at address 0x00000010: lui $s0, 0x1001 addi $t0, $zero, 42 sub $tl, $a0, $al ori $s0, $s0, 0x0040 beq $to, $a3, Exit addi $t4, $zero, 0 sll ?zero, $zero, 0 sw $to, (s0) Exit: # This label resolves to address 0x00000100