2. The following memory and cache memory is given. CPU generates addresses 0x1, 0x2,0x1, 0x8,0x9, 0x1C, 0x1D, 0x3, and 0x4. A. Show the contents of the cache using two way set associative mapping, assume a LRU replacement policy. B. What is the hit rate? Tag B1 BO L U V Tag B1 BOLRU Set Address v 000 Address Content 00000 00001 3 00010 00011 6 001007 00101 8 00110 9 00111 12 Address Content 10000 5 100010 100101 10011 11 10100 15 10101 09 10110 12 10111 23 11000 65 11001 21 11010 8 11011 7 11100 9 111010 11110 2 11111 5 01000 01001 010108 01011 01100 01101 01110 01111 3. A computer has 24 bit physical addresses and each memory location holds one byte. This computer has 64 cache lines and each line holds 16 bytes. Show the format of the address (tag, index, and byte offset) using A. Direct mapping. B. 4-way set associative C. 8-way set associative