2. The VHDL code given below is describing a block diagram of a circuit. Draw the architecture RTL that is described by this code.

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY variable_rotator is PORT( A : IN STD_LOGIC_VECTOR(15 downto 0); B : IN STD_LOGIC_VECTOR(3 downto 0); C : OUT STD_LOGIC_VECTOR(15 downto 0) ) END variable_rotator; ARCHITECTURE structural OF variable_rotator IS TYPE array16 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL A1 : array 16 SIGNAL Ar : array16; BEGIN Al(0)