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2 . Which language is commonly used for the formal description of electronic circuits? A ) C + + B ) Python C ) VHDL

2. Which language is commonly used for the formal description of electronic circuits?
A) C++
B) Python
C) VHDL
D) Java
3. What is the primary objective of using VHDL in digital circuit design?
A) Modeling circuits
B) Implementing hardware
C) Software development
D) Simulation testing
4. What is the key difference between HDLs and programming languages?
A) HDLs focus on software development
B) Programming languages describe hardware circuits
C) HDLs are used for circuit description, and not programming languages
D) Programming languages are used for simulation only
5. Which design rule is emphasized for complex designs?
A) Karnaugh maps
B) State minimization
C) Hierarchical design
D) Component reuse
6. What is the primary purpose of synthesizable VHDL?
A) Circuit modeling
B) Hardware implementation
C) Simulation testing
D) Software development
7. Which component is used to represent the interface of a circuit in VHDL?
A) Entity
B) Architecture
C) Signal
D) Component
8. What is the main limitation of VHDL?
A) Limited control on physical hardware layout VLSI
B) Analog circuit design
C) Easy syntax
D) Independent of synthesis tools

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