[20pts. 2- Consider the following code assuming the pipeline latencies shown below and a 1-cycle delay branch that is resolved in the ID stage. In addition, the pipeline uses MEM-to-ID forwarding to forward the result of an ALU operation from the MEM stage to the ID stage. ; C code for (i=100;i>0;i=i1) x[i]=x[i]+10 ; MIPS code loop: L.D F0, 0(R1);F0=array element ADD.D F4,FO,F2 ; Add scalar constant S.D 0(R1),F4; Store result DADDIU R1, R1, \#-8 ; Decrement array ptr. BNEZ R1, R2, loop ; Branch if R1!=R2 Latencies of FP operations (a) Show how this loop would execute without any scheduling. Maximize the performance of this code by applying both instruction reordering (also known as pipeline scheduling) and delay branch techniques. Ignoring the startup delays and assuming the loop executes 100 times, determine the number of cycles required to execute the code before and after the optimizations. Do not be concerned about what happens after the loop. (b) Unroll the loop three times (i.e., make four copies) to schedule it without stalls and show the instruction schedule. Again, determine the number of cycles required to execute the code before and after unrolling with scheduling