2-3. Model the D flip-flop with synchronous reset using behavioral modeling. Develop a testbench to test (generate input as shown) and validate the design. Simulate the design. Assign D input to SW0, reset to SW1, Clk to SW15, and output Q to LEDO. Verify the design in hardware. Name ck D 0 0 reset 0 0 Value 20 ns 40 ns 2-3-1. Open Vivado and create a blank project called lab5_2_3. 2-3-2. Create and add the Verilog module that will model the D flip-flop with synchronous reset. 2-3-3. Develop a testbench to test and analyze the design behavior. It should generate the input stimuli as shown in the timing diagram. 2-3-4. Add the appropriate board related master XDC file to the project and edit it to include the related pins, assigning D input to SWO, reset input to SW1, Clk to SW15, and Q to LEDO. set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets { clk }]; The above line of code needs to be added to the XDC file to allow SW15 be used as a clock. 2-3-5. Set the tcl.pre option in the Bitstream Settings to point to the provided lab5_prehook.tcl file. This file allows a combinatorial loop to be uploaded to the board. 2-3-6. Synthesize and implement the design. Look at the Project Summary and note that 1 BUFG and 4 IOs are used. The BUFG is used because the clock signal is used in the design. 2-3-7. Generate the bitstream, download it into the Basys3 or the Nexys4 DDR board, and verify the functionality. 180 n