2.Determine the delay (in terms of d) for each of the following 128-bit CLA designs when fan-in limit (f ) is set to each of the following: (

a) f = 3

(b) f = 7

3.In problem 2, if a modular CLA is first designed such that the most number of bits can be handled by such a modular circuit without having to extend the AND- OR levels in the carry lookahead circuit, the complete adder is then designed by cascading a number of such modular CLAs by rippling the carries between the modules. Determine the overall delay (in d) for each of the following cases:

(a) f = 3

(b) f = 7