3. [15] This question is regarding the textbook implementation of the MIPS 5-stage pipeline. Consider the following loop: loop:lw ?rl, 0 ($rl) and $rl, ?rl, $r2 Assume that . Branch is resolved at the ID stage and delayed branch is not used. A pipeline . The pipeline has full support of data forwarding, including that for the branclh * If no branch is involved, the pipeline stalls for one clock cycle on every load-use bubble occurs on every taken branch. instruction to receive register operands. data hazard If a branch is involved, the pipeline stalls for one clock cycle on every ALU data hazard, and two clock cycles on every load-use hazard. . b. [5] Assume that the loop is executed for N iterations, N> 1. How many clock cycles does it take to execute the loop? (Assume it is the number of clock cycles for all the instructions to pass the EX stage.) 3. [15] This question is regarding the textbook implementation of the MIPS 5-stage pipeline. Consider the following loop: loop:lw ?rl, 0 ($rl) and $rl, ?rl, $r2 Assume that . Branch is resolved at the ID stage and delayed branch is not used. A pipeline . The pipeline has full support of data forwarding, including that for the branclh * If no branch is involved, the pipeline stalls for one clock cycle on every load-use bubble occurs on every taken branch. instruction to receive register operands. data hazard If a branch is involved, the pipeline stalls for one clock cycle on every ALU data hazard, and two clock cycles on every load-use hazard. . b. [5] Assume that the loop is executed for N iterations, N> 1. How many clock cycles does it take to execute the loop? (Assume it is the number of clock cycles for all the instructions to pass the EX stage.)