Use the RTL design process to design a system that outputs the average of the most recent two data input samples. The system has an 8-bit unsigned data input I and an 8- bit unsigned output. The data input is sampled when a single bit control input S changes from 0 to 1. Choose internal bit widths so to prevent overflow. a. Capture the system behaviour by drawing the HLSM diagram of the machine. b. Design and draw the datapath for this design c. What are the signals in your datapath that needs to be connected to the controller? d. Draw the state diagram for the controller.