3. [6 pts] Let the individual stages of the MIPS datapath have the latencies listed below (please refer to the diagram of the MIPS datapath below) Instruction Fetch Instruction Decode Execute Memory Write-Back 340 ps 220 ps 320 ps 380 ps 260 ps (a) What is the clock cycle time (cct): i. For a single-cycle processor? ii. For a multi-cycle processor? (b) What is the total latency of a MIPS "addi" (add immediate) instruction: i. For a single-cycle processor? ii. For a multi-cycle processor? c) What is the total latency of two consecutive MIPS"addi" (add immediate) instructions: i. For a single-cycle processor? ii. For a multi-cycle processor? PCSIC ALU >Add result ALUSIC ALU operation Read address Read data 1 MemWrite Merto Reg Zero Instruction Registers Road ALU ALUAddress Read register 1 Read register 2 Write Re register Write data RegWrite Read data result Address Instruction memory Write data Data memory 16 Mem Read Sign- extend