$3 8. For a five-stage (IF, ID, EX, MEM, WB) pipelined datapath with forwarding and consider the following MIPS instruction sequence with initial values of $t1 = 1 and $t2 = 20, please answer the following questions. (10%) sw $t2, 20($s1) add $t2, $t1, $t1 add $t2, $t2, $t2 Iw $s3, 24($s1) add $t3, $s3, $t2 (a) Which register(s) is/are read in clock cycle 5? (3%) (b) What is the value of $12 at the end of clock cycle 6? (3%) (c) How many clock cycles are required to finish the execution of this instruction sequence? (4%) 46