3. (9 pts) Cache Design in terms of simple performance consideration. A pipelined processor with a separate instruction and data cache has five stages, a cycle time of 30 ns, and can start a new instruction on every cycle when there are no hazards It is used with a copy-back (write-back) data cache with a line size of one word, T_cache=30 ns, and T main = 80 ns. The hit rate in the cache is 90%. In this cache, a missed word is not passed to the processor until the entire line is received from main memory. Ignore write-backs of dirty pages. 25% of all instructions are performing LOADs and STORES (i.e., data reads and writes). For this problem, assume all other instructions cause no hazards and the LOAD and STORE instructions only stall because of memory access time. How many stalls occur when a memory access instruction misses in the cache? stalls What is the average instruction throughput (in IPS) of this processor? (show work) I/sec 3. (9 pts) Cache Design in terms of simple performance consideration. A pipelined processor with a separate instruction and data cache has five stages, a cycle time of 30 ns, and can start a new instruction on every cycle when there are no hazards It is used with a copy-back (write-back) data cache with a line size of one word, T_cache=30 ns, and T main = 80 ns. The hit rate in the cache is 90%. In this cache, a missed word is not passed to the processor until the entire line is received from main memory. Ignore write-backs of dirty pages. 25% of all instructions are performing LOADs and STORES (i.e., data reads and writes). For this problem, assume all other instructions cause no hazards and the LOAD and STORE instructions only stall because of memory access time. How many stalls occur when a memory access instruction misses in the cache? stalls What is the average instruction throughput (in IPS) of this processor? (show work) I/sec