$3.$ A circuit is implemented as f$=$ AB$+$A$$D

a$)$ Fill in the Karnaugh map.

b$)$ Draw the loops for the gates as implemented. Label them.

c$)$ Identify any static one hazards. If you use the map to indicate them, label them.

d$)$ Complete the timing diagram below for the original circuit. The inverter delays are $1$ns$,$and the other gates all have a delay of $2$ ns$.$ Did the hazard appear?

e$)$ What gate$($s$)$ would you add to fix the hazard? Draw the improved circuit, and Indicate which gate$($s$)$ is $($are$)$ new.

d$)$ Complete the timing diagram below for the original circuit. The inverter delays are $1$ ns$,$ and the other gates all have a delay of $2$ ns $.$ Did the hazard appear?

e$)$ What gate$($s$)$ would you add to fix the hazard? Draw the improved circuit, and indicate which gate$($s$)$ is $($are$)$ new.