3) A counter with RST (reset) and DIR (direction) entries will be designed. RST = 0 and DIR = 0 when (..0,2,4,0.. or ..1,3,5,1..) forward in twos in the form and RST = 0 and DIR = 1 when (...0,5,4,3,2,1,0,5 ...) will be a counter that counts down in the form. When RST=1 Regardless of the DIR, the counter will go to the value 0"and. It will remain there as long as RST=1. When RST=0, it will continue to Dir accordingly. Also, when the number is o OVR (Overflow.overflow) output will be 1 in other cases, it will be 0. a) how many Flip-flops will you need to use in your design? Please explain. b) create a state transition diagram and table for the system. c) if your student number is an odd number: using the system T flip-flops you will perform. Required next state logic circuit multiplexers perform using If your student number is an even number: using System D flip-flops you will perform. Required next state logic circuit multiplexers perform using. d) the frequency of the clock signal used in the counter is 300kHz and the counter is at "0" let's assume that. If your student number is an odd number: if RST=0 and DIR=0, the counter output is OVR calculate the time it takes for the value to be "1" again 10 times. If your student number is an even number: for the same time and status, if RST=0 and DIR=1 if the counter output is 10 times the time it takes for the OVR value to be "1" again calculate. 3) A counter with RST (reset) and DIR (direction) entries will be designed. RST = 0 and DIR = 0 when (..0,2,4,0.. or ..1,3,5,1..) forward in twos in the form and RST = 0 and DIR = 1 when (...0,5,4,3,2,1,0,5 ...) will be a counter that counts down in the form. When RST=1 Regardless of the DIR, the counter will go to the value 0"and. It will remain there as long as RST=1. When RST=0, it will continue to Dir accordingly. Also, when the number is o OVR (Overflow.overflow) output will be 1 in other cases, it will be 0. a) how many Flip-flops will you need to use in your design? Please explain. b) create a state transition diagram and table for the system. c) if your student number is an odd number: using the system T flip-flops you will perform. Required next state logic circuit multiplexers perform using If your student number is an even number: using System D flip-flops you will perform. Required next state logic circuit multiplexers perform using. d) the frequency of the clock signal used in the counter is 300kHz and the counter is at "0" let's assume that. If your student number is an odd number: if RST=0 and DIR=0, the counter output is OVR calculate the time it takes for the value to be "1" again 10 times. If your student number is an even number: for the same time and status, if RST=0 and DIR=1 if the counter output is 10 times the time it takes for the OVR value to be "1" again calculate