3- An implementation of a processor's datapath has the following latencie:s PC 20 ps 200 ps 70 ps 20 ps 90 ps Consider the following figure for the processor's datapath. I-MemAddMux ALURe RegsD-MemControl 90ps250 ps 40 ps IMI Add ALU Shift left 2 ead MemtoR Instruction 131-26) Control Instruction [25-21] Read register 1 Read Instruction [20-16 Rea data 1 M Write data 2 Read PCaddress Zero ALU ALU register 2 31-0] resultAddress Read Instruction Instruction [15-11x 11register MI data Registers Data data Instruction [15-0] 16 sign 32 ALU (a) What is the critical path for a MIPS BEQ instruction in this implementation? (b) What would be the cycle time for this critical path for the single cycle implementation? 3- An implementation of a processor's datapath has the following latencie:s PC 20 ps 200 ps 70 ps 20 ps 90 ps Consider the following figure for the processor's datapath. I-MemAddMux ALURe RegsD-MemControl 90ps250 ps 40 ps IMI Add ALU Shift left 2 ead MemtoR Instruction 131-26) Control Instruction [25-21] Read register 1 Read Instruction [20-16 Rea data 1 M Write data 2 Read PCaddress Zero ALU ALU register 2 31-0] resultAddress Read Instruction Instruction [15-11x 11register MI data Registers Data data Instruction [15-0] 16 sign 32 ALU (a) What is the critical path for a MIPS BEQ instruction in this implementation? (b) What would be the cycle time for this critical path for the single cycle implementation