.3 By convention, a cache is named according to the amount of data it contain a 4 KIB cache can hold4 KB of data): howeves, caches also require SRAM t More metadata such as tags and valld bits For this exercise, you will examine how a caches configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses and words are 64 its 5.3.1 [10 Generate a series of read requests that have a lower miss rate on a 32 KIB two- way set associative cache than on the cache described in Exercise 5.3.1 .3 By convention, a cache is named according to the amount of data it contain a 4 KIB cache can hold4 KB of data): howeves, caches also require SRAM t More metadata such as tags and valld bits For this exercise, you will examine how a caches configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses and words are 64 its 5.3.1 [10 Generate a series of read requests that have a lower miss rate on a 32 KIB two- way set associative cache than on the cache described in Exercise 5.3.1