3. Consider the following circuit. Assume timings for both D flip-flops are identical with below values: D flip-flop Setup time = TS = 10 ps D flip-flop Hold time = TH = 15 ps D flip-flop Clock-to-Q delay = TQ = 60 ps Combinational Logic Delay = Td = 20 ps t=0 DFF-1 D Q1 New D Data Input DFF >C Clock Combinational Logic DFF-2 D2 D Out DFF Td Time delay >C Q* Wire Delay c) Compute the new data input uncertainty time interval (aperture time TA). d) How long does it take for D flip-flop to process each new data? e) What is the earliest time that the rising edge of clock can be asserted for the new input data to be processed by DFF-1? f) What is the earliest time that the output data of the first flip-flop (DFF-1) is valid at the input of the combinational logic? g) If there is no wire delay, what is the minimum clock period? h) What is the maximum acceptable wire delay (clock skew)?