3. Consider the gate-level circuit in the figure. (a) Determine the function of the circuit. [AB] (b) Draw an equivalent complementary CMOS transistor circuit. (c) Size the transistors in part (b) such that each NAND gate has similar output resistance to that of an inverter with W/W.= 2/1. [W, = W. - 2] (d) Based on your circuit in part (b) above, calculate the logical effort, g for inputs A and B for the circuit. [ga-gB= 4/3] (e) Based on your circuit in part (b) above, calculate the total intrinsic path delay, P= Ep; for the circuit. [p = 2, P = 6] : De