3. Draw a block diagram of the hardware to implement the following RTL statements: : R3-R1+R2 Cc: R34-R3+1 (transfer addition of RI and R2 into R3) (increment R3) 4. Using two 4-bit registers R1 and R2, and AND gates, OR gates and inverters, draw one bit slice of the logic diagram that implements all of the following statements: Co: R24-0 (clear R2 synchronously with the clock) CI: R2e-RI (transfer contents of R1 to R2) C2: R24-R2 (complement contents of R2) NOTE: The control variables are mutually exclusive i.e. only one variable can asserted (equal to 1, since they are all active high) at any time. Also, no transfer into R2 is to occur for all control variables de-asserted