(3 pts) Derive the states corresponding to the FSM description as a state diagram. Show all possible states, as well as the conditions which move the circuit from one state to the next. 2. (3 pts) Derive the state table from the state transition diagram. Confirm that there are no redundant states; if there are, optimize the state table and regenerate the diagram. 3. (3 pts) Assign states and derive the equations for the flip flop inputs. Try with both D and JK flip flops. Choose the one that requires the fewest number of ICs. Remember to consider any "don't cares" which can further optimize the logic