3. Suppose we have a system with three level of caches: Ll is close to the processor, level 2 is below it, and level 3 is the last level before accessing the main memory. We know that two main characteristics of a cache performance are: cache access latency (How long does the cache take before responding with hit or miss?) and cache hit rate (how many of the cache accesses are hits?). As we go from Ll to L2 to L3, which of the two characteristics become more important? and why