$4\mathrm{.}15$ lw is the instruction with the longest latency on the CPU from

Section $4\mathrm{.}4.$ If we modified lw and sw so that there was no offset $($i$.$e$.,$ the

address to be loaded from$/$stored to must be calculated and placed in rs

before calling lw$/$sw$),$ then no instruction would use both the ALU and

Data memory. This would allow us to reduce the clock cycle time.

However, it would also increase the number of instructions, because

many ld and sd instructions would need to be replaced with lw$/$add or

sw$/$add combinations.

$4\mathrm{.}15\mathrm{.}1[5]<4\mathrm{.}4>$ What would the new clock cycle time be$?$

$4\mathrm{.}15\mathrm{.}2[10]<4\mathrm{.}4>$ Would a program with the instruction mix

presented in Exercise $4\mathrm{.}7$ run faster or slower on this new CPU? By

how much? $($For simplicity, assume every lw and sw instruction is

replaced with a sequence of two instructions.$)$

$4\mathrm{.}15\mathrm{.}3[5]<4\mathrm{.}4>$ What is the primary factor that influences whether

a program will run faster or slower on the new CPU?

$4\mathrm{.}15\mathrm{.}4[5]<4\mathrm{.}4>$ Do you consider the original CPU $($as shown in

Figure $4\mathrm{.}21)$ a be