4. [10, 12, 13, 11, 4, 10, 5, 42, 41, 4, 43, 40, 9, 8] represent these accesses to a memory cache, size 128Bytes, 2 words per block, in these two cases: direct mapped and 2-way set associative. Show the status of the cache after the accesses. Show the number of hits, and calculate the hit and miss rate