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4. (40 points) Size the following circuit using LE and determine the total delay and size of each gate when Coff-path =0, Coff-path=5, Coff-path
4. (40 points) Size the following circuit using LE and determine the total delay and size of each gate when Coff-path =0, Coff-path=5, Coff-path 30 and Coff-path = 120. a. Use the non-iterative solution method. Ignore the off-path capacitance and size the circuit using LE. Then, add the off-path capacitance to calculate the delays. Don't change the initial sizing of each gate. b. Use iterative solution. Iteratively size each gate (C2, C3 and C4) to reduce the total delay. Start with Coff-path =0 solution and iteratively solve for other cases. c. Report the differences between iterative and non-iterative solution in terms of path delays. ID C = 1 Cz C4 Coff-path H 64
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Digital Systems Design Using Verilog
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
1st edition
1285051076, 978-1285051079
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